M306H7MG-XXXFP Datasheet, PDF (40/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Main clock oscillation
High-speed mode
CPU clock: f(XIN)
CM07=0
CM06=0
CM17=0
CM16=0
Middle-speed mode Middle-speed mode
(divide by 2)
(divide by 4)
CPU clock: f(XIN)/2
CM07=0
CM06=0
CM17=0
CM16=1
CPU clock: f(XIN)/4
CM07=0
CM06=0
CM17=1
CM16=0
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/8
CM07=0
CM06=1
CPU clock: f(XIN)/16
CM07=0
CM06=0
CM17=1
CM16=1
CM04=1
CM04=0
High-speed mode
CPU clock: f(XIN)
CM07=0
CM06=0
CM17=0
CM16=0
Middle-speed mode Middle-speed mode Middle-speed mode Middle-speed mode
(divide by 2)
(divide by 4)
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/2
CM07=0
CM06=0
CM17=0
CM16=1
CPU clock: f(XIN)/4
CM07=0
CM06=0
CM17=1
CM16=0
CPU clock: f(XIN)/8
CM07=0
CM06=1
CPU clock: f(XIN)/16
CM07=0
CM06=0
CM17=1
CM16=1
CM07=1
(Note 2)
Low-speed mode
CPU clock: f(XCIN)
CM07=0
CM07=0
(Note 1, Note 3)
CM05=1
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Switch clock after oscillation of main clock is sufficiently stable.
2: Switch clock after oscillation of sub-clock is sufficiently stable.
3: Change CM17 and CM16 before changing CM06.
4: Transit in accordance with arrow.
Figure 4.9 State Transition in Normal Mode
Rev.2.10 Oct 25, 2006 Page 40 of 326
REJ03B0152-0210