M306H7MG-XXXFP Datasheet, PDF (184/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
14.3 Slice RAM
Slice RAM stores 18-line slice data. There are several types of Slice data : PDC, VPS, VBI, XDS, WSS, etc. All
data are stored to addresses which corresponds to slice line (ex. 22 line' data is stored to addresses 20016 to 21716 ).
24 addresses (SR00x to SR17x) are prepared for 1 line, slice data is stored in order from LSB side. Then, slice data
type and field information are stored to the top address of each line.
Slice RAM composition is shown in Table 14.2.
Table 14.2 Slice RAM composition
Slice RAM addresses
(SA9 to SA0)
SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8
SD7 SD6 SD5
SD4 SD3
SD2 SD1 SD0 Remarks (Note1)
00016
00116
to
01616
01716
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 6th line or 318th line
SR01F SR01E SR01D SR01C SR01B SR01A SR019 SR018 SR017 SR016 SR015 SR014 SR013 SR012 SR011 SR010 slice data
to to to to to to to to to to to to to to to to
SR16F SR16E SR16D SR16C SR16B SR16A SR169 SR168 SR167 SR166 SR165 SR164 SR163 SR162 SR161 SR160
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
01816
to
01F16
02016
to
03716
04016
to
1F716
20016
to
21716
22016
to
23716
Unused area
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 7th line or 319th line
to
to to
to to
to to
to to
to to
to
to
to
to
to slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
8th line to 21th line
or 320th line to 333 line
slice data
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 22th line or 334th line
to
to to
to to
to to
to to
to to
to
to
to
to to slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 23th line or 335th line
to
to to
to to
to to
to
to
to to
to
to
to
to
to slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
Note 1. This is the line to support when the PAL video signal is sliced and setting the expansion registers to VPS_VP8 to VPS_VP0
(bits 8 to 0 in address 2916) = "416".
For accessing to Slice RAM data, set accessing address (SA9 to SA0) (shown in Table 14.2) to Slice RAM address
control register (address 020E16 ). Then read out data from Slice RAM data control register (address 021016 ).
When end the data reading, Slice RAM address control register increments address automatically. Then, next
address data reading is possible. Do not access to unused area of each character codes. Must set address to each line
because unused area has no address' automatically increment.
Slice RAM bit composition is shown in Figure 14.2, Slice RAM access registers are shown in Figure14.3 and Slice
RAM access block diagram is shown in Figure 14.4
Rev.2.10 Oct 25, 2006 Page 184 of 326
REJ03B0152-0210