M306H7MG-XXXFP Datasheet, PDF (133/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.7 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented,
and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 10.17 lists the specifications of SIM mode. Table 10.18 lists the registers used in the SIM mode and the
register values set.
Table 10.17 SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
(Note 2)
Error detection
Specification
• Direct format
• Inverse format
• U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register 0016 to FF16
• Before transmission can start, the following requirements must be met
_ _{The TE bit of U2C1 register= 1 (transmission enabled)}
_ _{The TI bit of U2C1 register = 0 (data present in U2TB register)}
• Before reception can start, the following requirements must be met
_ _{The RE bit of U2C1 register= 1 (reception enabled)}
_ _{Start bit detection}
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmis-
sion complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
Rev.2.10 Oct 25, 2006 Page 133 of 326
REJ03B0152-0210