M306H7MG-XXXFP Datasheet, PDF (242/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
(4) Remote control pattern recognition
Pattern matching of remote control is performed using a sub clock oscillation. Remote control input is input from
RMTIN terminal. Interruption is generated when pattern matching is in agreement.
4 times match noise filter is being included, in front of the pattern matching circuit. A block diagram is shown in
Figure 14.15.
The example of a waveform of pattern matching is shown in Figure.14.16. The flow of pattern matching is shown
in Figure.14.17.
Sub clock fc
FILDIV1(1, 0)
bit
divider _FILDIV0
bit
divider for
B/D period
P94/TB4in
/RMTin
Four time
agreement
Filter
FILON
bit
Port 94
Input buffer
Polarity Header pattern
selection match circuit
Interruption
Control
Timer B4/remote control
interrupt request
RMTSEL
bit
A period:RMTHD0
B period:YUKOU0
C period:RMTHD1
D period:YUKOU1
INTRMT3 to 0
bit
Timer B4
Timer B4 interrupt
Figure 14.15 Remote control pattern recognition block diagram
RMTIN
B
D
A
C
Header
0 data
1 data
The number of registers At maximum check time
A
"L" check programmable
9 bit
15.6 ms
B
Check of a rising edge
6 bit
3.8 ms (Note 2)
C
"H" check programmable
9 bit
15.6 ms
D
Check of a falling edge
6 bit
3.8 ms (Note 2)
Note 1. 1bit unit 32.768kHz (a part for one clock)
Note 2. The maximum check period of B and D is the values when enhancing register FILDIV0
(Address 3316) is set to "1".
Figure 14.16 Example of waveform of pattern matching
Rev.2.10 Oct 25, 2006 Page 242 of 326
REJ03B0152-0210