M306H7MG-XXXFP Datasheet, PDF (243/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
Initial pulse waiting state
Detect a
No
falling edge?
Yes
Retain
the "L" state
No
during A?
Yes
Detect
a rising edge
No
during B?
Yes
Retain
the "H" state
No
during C?
Yes
Detect
a falling edge
No
during D?
Yes
Interruption generating
Figure 14.17 Flow of pattern matching
4 times match process operation
This is a 4 times match digital filter using the sub clock oscillation. The input signal of the RMTin pin is sampled
4 times and the output level will change only when the level matches 4 times. When using this filter, set the
FILON bit (bit11) in the expansion register 33H to "1". The signal after passing 4 times match filter is applied to
the header pattern matching circuit and timer B4 at filter ON. The sampling rate can be changed by the FILDIV1
(1, 0) bit in the expansion register 33H. Refer to the FILDIV1 bit of the expansion register 33H function
description for details. The input signal is through supplied to the latter circuit at filter OFF. (no clock
delay).Since this filter operates only with the sub clock and cannot be used for the main clock, set the filter to OFF
(FILON bit ="0") when the sub clock is not mounted.
(5) Clock timer function
The sub clock is selected as the count source and the clock timer can set and read the count value every day,
minute and second. It has the following functions.
Clock function
1.This timer is dedicated clock function which is independent from timer A and timer B.
2.The settable ranges of day, minute and second are 0 to 65535 days, 0 to 1439 minutes and 0 to 59 seconds.
3.Second just setting is available (reset the count value of less than second).
1 second interrupt
1.The interrupt request is generated when second of the clock timer is incremented.
(The interrupt request is not generated at the second just setting.)
Rev.2.10 Oct 25, 2006 Page 243 of 326
REJ03B0152-0210