M306H7MG-XXXFP Datasheet, PDF (91/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
9.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 9.8). Figure 9.19 shows TBiMR register in pulse period and pulse width measurement
mode. Figure 9.20 shows the operation timing when measuring a pulse period. Figure 9.21 shows the operation
timing when measuring a pulse width.
Table 9.8 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Specification
Count source
f1, f2, f8, f32, fC32
Count operation
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
Count start condition
surement pulse. The counter value is set to “000016” to continue counting.
Set TBiS (i=0 to 5) bit³ to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input¹
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function
Read from timer
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading TBi register²
Write to timer
Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned
to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039B16 to 039D16
035B16 to 035D16
After reset
00XX00002
00XX00002
Bit symbol
Bit name
Function
RW
TMOD0 Operation mode
b1 b0
1 0 : Pulse period / pulse width
RW
select bit
TMOD1
measurement mode
RW
MR0
Measurement mode
select bit
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
RW
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
MR1
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
RW
a rising edge and the next falling edge)
1 1 : Must not be set.
MR2
TB0MR and TB3MR registers
RW
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
MR3
Timer Bi overflow
flag ( Note)
0 : Timer did not overflow
1 : Timer has overflowed
RO
TCK0
Count source
select bit
b7 b6
0 0 : f1 or f2
0 1 : f8
RW
TCK1
1 0 : f32
1 1 : fC32
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register's bit 5 to bit 7.
Figure 9.19 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.2.10 Oct 25, 2006 Page 91 of 326
REJ03B0152-0210