M306H7MG-XXXFP Datasheet, PDF (129/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.5.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register’s
CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
• Master (Internal Clock)
Figure 10.26 shows the transmission and reception timing in master (internal clock).
• Slave (External Clock)
Figure 10.27 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 10.28 shows the transmission and reception timing (CKPH=1) in slave (external clock).
Clock output
"H"
(CKPOL=0, CKPH=0) ^"L"
Clock output
"H"
(CKPOL=1, CKPH=0) _"L"
Clock output
"H"
(CKPOL=0, CKPH=1) _"L"
Clock output
"H"
(CKPOL=1, CKPH=1) "L"
Data output timing ^"H"
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 10.26 Transmission and Reception Timing in Master Mode (Internal Clock)
Rev.2.10 Oct 25, 2006 Page 129 of 326
REJ03B0152-0210