M306H7MG-XXXFP Datasheet, PDF (52/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.10 Interrupt Response Time
Figure 6.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time
from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
Specifically, it consists of a time from when an interrupt request is generated till when the instruction then
executing is completed ((a) in Figure 6.5) and a time during which the interrupt sequence is executed ((b) in Figure
6.5).
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Time
Instruction in
interrupt routine
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Figure 6.5
Interrupt vector address SP value 16-Bit bus, without wait
Even
Even
18 cycles
Even
Odd
19 cycles
Odd
Even
19 cycles
Odd
Odd
20 cycles
8-Bit bus, without wait
20 cycles
20 cycles
20 cycles
20 cycles
Interrupt response time
6.11 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table
6.5 is set in the IPL. Shown in Table 6.5 are the IPL values of software and special interrupts when they are
accepted.
Table 6.5 IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Level that is set to IPL
Watchdog timer, NMI
Software, address match, DBC, single-step
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Rev.2.10 Oct 25, 2006 Page 52 of 326
REJ03B0152-0210