M306H7MG-XXXFP Datasheet, PDF (281/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
17. FLASH MEMORY VERSION
17.2 Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 17.1 shows the block diagram of flash momoery.
The user ROM area is divided into several blocks, each of which can individually be protected (locked) against
programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial input/output,
and parallel input/output modes.
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in parallel
input/output mode. After a hardware reset that is performed by applying a high-level signal to the CNVSS and P50
pins and a low-level signal to the M1 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the user
ROM area is executed (but the boot ROM area cannot be read).
0C000016
Block 8 : 64K bytes
0F000016
0D000016
Block 7 : 64K bytes
Block 5 : 32K bytes
0E000016
0F7FFF16
0F800016
0EFFFF16
0F000016
Block 6 : 64K bytes
0F9FFF16
0FA00016
0FBFFF16
0FC00016
0FFFFF16
Block 0 to Block 5 (32+8+8+8
+4+4)K bytes
0FDFFF16
0FE00016
0FEFFF16
0FF00016
0FFFFF16
User ROM area
Block 4 : 8K bytes
Block 3 : 8K bytes
Block 2 : 8K bytes
Block 1 : 4K bytes
Block 0 : 4K bytes
Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Figure 17.1 Flash Memory Block Diagram
0FF00016
0FFFFF16
4K bytes
Boot ROM area (Note 1)
Rev.2.10 Oct 25, 2006 Page 281 of 326
REJ03B0152-0210