M306H7MG-XXXFP Datasheet, PDF (136/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.31 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
TxD2
RxD2
SIM card
Figure 10.31 SIM Interface Connection
10.7.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved by
pulling the TxD2 output low with the timing shown in Figure 10.32. If the U2RB register is read while
outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output is
returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that
immediately follows the stop bit. Therefore, whether a parity signal has been returned can be determined by
reading the port that shares the RxD2 pin in a transmission-finished interrupt service routine.
Transfer “H”
clock “L”
RxD2 “H”
“L”
ST D0 D1 D2 D3 D4 D5 D6 D7
TxD2 “H”
“L”
(Note)
U2C1 register “1”
RI bit “0”
This timing diagram applies to the case where the direct format is
implemented.
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
P SP
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 10.32 Parity Error Signal Output Timing
Rev.2.10 Oct 25, 2006 Page 136 of 326
REJ03B0152-0210