M306H7MG-XXXFP Datasheet, PDF (57/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.16 INT Interrupt
INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR
register's IFSRi bit.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the IFSR
register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
INT2 and the remote control transmission, the vector and the interrupt control register are shared. (Please refer to
“14. Expansion Function” for details. )
Figure 6.10 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
IFSR0
Bit name
INT0 interrupt polarity
switching bit
Function
RW
0 : One edge
1 : Both edges (Note 1)
RW
IFSR1
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
IFSR2
IFSR3
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
0 : One edge
1 : Both edges (Note 1)
RW
IFSR4
IFSR5
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges _{(Note 1)}
RW
0 : One edge
1 : Both edges (Note 1)
RW
IFSR6
Interrupt request cause
select bit
0 : SI/O3 _{(Note 2)}
1 : INT4
RW
IFSR7
Interrupt request cause
select bit
0 : SI/O4 _{(Note 2)}
1 : INT5
RW
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035E16
After reset
00XXXXXX2
Bit symbol
Bit name
Function
RW
(b5-b0)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
IFSR26
IFSR27
Interrupt request cause
select bit (Note 1)
Interrupt request cause
select bit (Note 2)
0 : Timer B3/HINT
1 : UART0 bus collision
RW
detection
0 : Timer B4/Remote control
1 : UART1 bus collision
RW
detection
Note 1: Timer B3/HINT and UART0 bus collision detection share the vector and interrupt control register. When using
the timer B3/HINT interrupt, clear the IFSR26 bit to “0” (timer B3/HINT). When using UART0 bus collision
detection, set the IFSR26 bit to “1”.
Note 2: Timer B4/Remote control and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4/Remote control interrupt, clear the IFSR27 bit to “0” (timer B4/Remote control).
When using UART1 bus collision detection, set the IFSR27 bit to “1”.
Figure 6.10 IFSR Register and IFSR2A Register
Rev.2.10 Oct 25, 2006 Page 57 of 326
REJ03B0152-0210