M306H7MG-XXXFP Datasheet, PDF (159/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK
return mode is shown below.
(1) Set a slave address in the high-order 7 bits of the I²C address register and “0” in the RBW bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I²C clock control register.
(3) Set “1016” in the I²C status register and hold the SCL at the HIGH.
(4) Set a communication enable status by setting “0816” in the I²C control register.
(5) Set the address data of the destination of transmission in the high-order 7 bits of the I²C data shift register and
set “0” in the least significant bit.
(6) Set “F016” in the I²C status register to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occurs.
(7) Set transmit data in the I²C data shift register. At this time, an SCL and an ACK clock automatically occurs.
(8) When transmitting control data of more than 1 byte, repeat step (7).
(9) Set “D016” in the I²C status register. After this, if ACK is not returned or transmission ends, a STOP condition
will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-
return mode, using the addressing format, is shown below.
(1) Set a slave address in the high-order 7 bits of the I2C address register and “0” in the RBW bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I²C clock control register.
(3) Set “1016” in the I²C status register and hold the SCL at the HIGH.
(4) Set a communication enable status by setting “0816” in the I²C control register.
(5) When a START condition is received, an address comparison is made.
(6)
•When all transmitted address are“0” (general call):
AD0 of the I²C status register is set to “1”and an interrupt request signal occurs.
•When the transmitted addresses match the address set in (1):
ASS of the I²C status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I²C status register are set to “0” and no interrupt request signal occurs.
(7) Set dummy data in the I²C data shift register.
(8) When receiving control data of more than 1 byte, repeat step (7).
(9) When a STOP condition is detected, the communication ends.
Rev.2.10 Oct 25, 2006 Page 159 of 326
REJ03B0152-0210