M306H7MG-XXXFP Datasheet, PDF (156/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(7) START condition generation method
When the ESO bit of the I²C control register is “1,” execute a write instruction to the I²C status register to set the
MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes
“0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are
different in the standard clock mode and the high-speed clock mode. Refer to Figure 11.10 for the START
condition generation timing diagram, and Table 11.2 for the START condition/STOP condition generation timing
table.
I²Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Set time
for BB flag
Figure 11.10 START condition generation timing diagram
(8) STOP condition generation method
When the ESO bit of the I²C control register is “1,” execute a write instruction to the I²C status register for setting
the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP
condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 11.11 for the STOP condition generation timing diagram, and Table 11.2 for
the START condition/STOP condition generation timing table.
I²Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time
for
BB flag
Figure 11.11 STOP condition generation timing diagram
Table 11.2 START condition/STOP condition generation timing table
Item
Setup time (Min.)
Hold time (Min.)
Set/reset time for BB flag
Standard Clock Mode
5.6 µs
4.8 µs
3.5 µs
High-speed Clock Mode
2.1 µs
2.3 µs
0.75 µs
Rev.2.10 Oct 25, 2006 Page 156 of 326
REJ03B0152-0210