M306H7MG-XXXFP Datasheet, PDF (154/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
• Bit 4: I²C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes
from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in
synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an
interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP
condition in slave, the multi-master I²C-BUS interface interrupt request bit (IR) is set to “1” (interrupt requested)
regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is
disabled. Figure 11.9 shows an interrupt request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Writing “1” to the PIN bit
• Executing a write instruction to the I²C data shift register or the I²C transmit buffer register (See note).
• When the ESO bit is “0”
• At reset
Note: It takes 12 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed to these
registers.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
• Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a
START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a
START condition is disabled by the START condition duplication prevention function (See note).
This flag cannot be written with software. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the ESO bit of the I²C control register is “0” and at
reset, the BB flag is kept in the “0” state.
• Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is
selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected
and address data and control data are output into the SDA in synchronization with the clock generated on the
SCL.
When the ALS bit of the I²C control register is “0” in the slave reception mode is selected, the TRX bit is set to
“1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master is “1.” When the
ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurrence of a START condition is disabled by the START condition duplication prevention function
(Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
Rev.2.10 Oct 25, 2006 Page 154 of 326
REJ03B0152-0210