M306H7MG-XXXFP Datasheet, PDF (320/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.9 Precautions for Programmable I/O Ports
(1) Setting the SM32 bit in the S3C register to “1” causes the P92 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P96 pin to go to a high-impedance
state.
(2) The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input
level at this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor
“low”), the input level may be determined differently depending on which side−the programmable input/
output port or the peripheral function−is currently selected.
19.10 Electric Characteristic Differences Between Mask ROM and Flash Memory
Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin,
noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the
flush memory version.
19.11 Precautions for Flash Memory Version
19.11.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and
0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard
serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash memory
cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of
fixed vectors.
19.11.2 Precautions for Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10
bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop mode)
Example program
L1:
BSET
JMP.B
0, CM
L1
1 ; Stop mode
Program after returning from stop mode
Rev.2.10 Oct 25, 2006 Page 320 of 326
REJ03B0152-0210