M306H7MG-XXXFP Datasheet, PDF (117/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
SDAi
Delay
circuit
STSPSEL=1
STSPSEL=0
ACK=1 ACK=0
ACKD register
Noise
Filter
SDHI _ALS
D _{Q Arbitration}
T
Start condition
detection
Stop condition
detection
Start and stop condition generation block
SDASTSP
SCLSTSP
Transmission
register
UARTi
IICM2=1
IICM=1 and
IICM2=0
Reception register
UARTi
S
Q
Bus
R _busy
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
DMA0
(UART0, UART2)
UARTi receive,
ACK interrupt request,
DMA1 request
SCLi
Noise
Filter
Falling edge
detection
IICM=0
R Port register
I/O port _Q (Note)
STSPSEL=0 ^{Internal clock}
DQ
T
DQ
T
9th bit
IICM=1UARTi
STSPSEL=1
SWC2
External
clock
CLK
control
UARTi
ACK
Start/stop condition detection
interrupt request
R
9th bit falling edge
S
SWC
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM
: UiSMR register bit
IICM2, SWC, ALS, SWC2, SDHI : UiSMR2 register bit
STSPSEL, ACKD, ACKC
: UiSMR4 register bit
i=0 to 2
Note: If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 10.21 I²C Mode Block Diagram
Rev.2.10 Oct 25, 2006 Page 117 of 326
REJ03B0152-0210