M306H7MG-XXXFP Datasheet, PDF (131/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.6 Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 10.16 lists the registers used in IE mode and the register values set. Figure 10.29 shows the functions of bus
collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect function.
Table 10.16 Registers to Be Used and Settings in IE Mode
Register
UiTB
UiRB(Note3)
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
Bit
0 to 8
0 to 8
OER,FER,PER,SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS (Note 1)
UiRRM (Note 1),
UiLCH, UiERE
0 to 3, 7
ABSCS
ACSE
SSS
0 to 7
0 to 7
0 to 7
IFSR26, IFSR27
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1,RCSP,7
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TxD/RxD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TxDi pin output mode (Note 2)
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Note 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IEmode.
i= 0 to 2
Rev.2.10 Oct 25, 2006 Page 131 of 326
REJ03B0152-0210