M306H7MG-XXXFP Datasheet, PDF (220/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
27. Address 2816 (=DA5 to 0)
DD15
0 0 00 0
DD8DD7
DD0
0
Bit symbol
ADLAT
START
Bit name
Function
Data acquisition selection bit ^{0 Acquisition of slice data}
1 Acquisition of A/D data
RW
Slice data selection bit
Turning on the output after slice RAM
of Flaming code detection position (8 bits)
and the average of the clock run-in level
(8 bits)and turning off are set (note.)
Reserved bit
Must set to "0."
×
6BITOFF ^{A/D lower bit selection bit}
0 Normal
1 Stop by 6th bit of A/D
Reserved bit
Must set to "1" when EPG-J is acquired. _×
Otherwise, set to "0."
SYNLVL0
SYNLVL1
SYNLVL2
ADON
INTAD
INTDA
Synchronous signal slice
level control bit
SYNLVL2 SYNLVL1 SYNLVL0 Slice level
0
0
0 approx.1.10V±0.10V
0
0
1 approx.1.15V±0.10V
0
1
0 approx.1.20V±0.10V
0
1
1 approx.1.25V±0.10V
1
0
0 approx.1.30V±0.10V
1
0
1 approx.1.35V±0.10V
1
1
0 approx.1.40V±0.10V
1
1
1 approx.1.45V±0.10V
Data slicer control bit
0
Data slicer OFF.
(The amplifier for slicer is also turned off).
1
Data slicer ON (see INTAD and the INTDA
about the amplifier for slicer)
The amplifier control bit for
data slicers
0 Always data slicer ON.
1
On 3 to 23 lines and 315 to 335 line amplifier ON.
On other line amplifier OFF
The rudder resistance control ^{0 Always ladder resistance for data slicer ON.}
bit for data slicers
1
On 3 to 23 lines and 315 to 335 line Ladder resistance
ON. On other line Ladder resistance OFF
Reserved bits
Must set to "0."
×
Note. Slice RAM: Refer to Figure "Slice RAM bit construction"
SR010 to SR01F
SR030 to SR03F
SR000 to SR00F
SR020 to SR02F
0 : Slice data Data1
Data2 Data3
SR010 to SR01F
SR000 to SR00F
SR020 to SR02F SR030 to SR03F
1 : Slice data
Data1
Data2
Flaming code detection location Clock run-in average level
(8 bits) (8 bits)
Rev.2.10 Oct 25, 2006 Page 220 of 326
REJ03B0152-0210