M306H7MG-XXXFP Datasheet, PDF (113/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
“1”
“0”
Start bit
Stop bit
D0
D1 D7
Sampled “L”
Receive data taken in
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive
register to UiRB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 10.16 Receive Operation
10.3.1 LSB First/MSB First Select Function
As shown in Figure 10.17, use the UiC0 register’s UFORM bit to select the transfer format. This function is
valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
RXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 10.17 Transfer Format
Rev.2.10 Oct 25, 2006 Page 113 of 326
REJ03B0152-0210