M306H7MG-XXXFP Datasheet, PDF (135/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
(1) Transmission
Tc
Transfer clock
U2C1 register ^{“1”}
TE bit _{“0”}
U2C1 register ^{“1”}
TI bit
“0”
TxD2
Parity error signal sent
back from receiver
RxD2 pin level
(Note)
U2C0 register ^{“1”}
TXEPT bit _{“0”}
S2TIC register ^{“1”}
IR bit _{“0”}
Write data to U2TB register
Transferred from U2TB register to UART2 transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P _SP
An “L” level returns due to the
occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P
The level is detected by the
SP
interrupt routine.
The IR bit is set to “1” at the
falling edge of transfer clock
The level is
detected by the
interrupt routine.
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is transferred in
the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal
sent back from receiver.
(1) Reception
Transfer clock
U2C1 register “1”
RE bit _{“0”}
Transmitter's
transmit waveform
TxD2
RxD2 pin level
(Note)
U2C0 register “1”
RI bit _{“0”}
S2RIC register “1”
IR bit
“0”
Tc
Start
bit
ParityStop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An “L” level is output from TxD2 due to
the occurrence of a parity error
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
Read the U2RB register
Read the U2RB register
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is received in
direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Figure 10.30 Transmit and Receive Timing in SIM Mode
Rev.2.10 Oct 25, 2006 Page 135 of 326
REJ03B0152-0210