M306H7MG-XXXFP Datasheet, PDF (45/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
• Special Interrupts
Special interrupts are non-maskable interrupts.
(1) NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about
the NMI interrupt, refer to the section "NMI interrupt".
(2) DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support tools.
(3) Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the
watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
(4) Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support tools.
(5) Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated
by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or AIER1 bit or the
AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details about the
address match interrupt, refer to the section "address match interrupt".
• Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 6.2. For details about the
peripheral functions, refer to the description of each peripheral function in this manual.
Rev.2.10 Oct 25, 2006 Page 45 of 326
REJ03B0152-0210