M306H7MG-XXXFP Datasheet, PDF (283/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
17. FLASH MEMORY VERSION
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
1111
Symbol
ROMCP
Address
0FFFFF16
Value when shipped
FF16 (Note 4)
Bit symbol
Bit name
Function
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
ROMCR ^{ROM code protect reset}
bit (Note 2, Note 4)
b5 b4
00: Removes protect
} ^01:
10: Enables ROMCP1 bit
11:
RW
RW
ROMCP1 ^{ROM code protect level}
1 set bit
(Note 1, Note 3, Note 4)
b7 b6
} ^00:
01: Protect enabled
RW
10:
11: Protect disabled
RW
Note 1: If the ROMCR bits are set to other than "002"and the ROMCP1 bits are set to other than "112"
(ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to "002," ROM code protect level 1 is removed. However, because the
ROMCR bits cannot be modified during parallel input/output mode, they need to be modified in
standard serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are "012," "102," or "112."
Note 4: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to "FF16."
Figure 17.2 ROMCP Register
Address
0FFFDF16 to 0FFFDC16 ID1
Undefined instruction vector
0FFFE316 to 0FFFE016 ID2
Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB16 to 0FFFE816 ^ID3
Address match vector
0FFFEF16 to 0FFFEC16 ID4
Single step vector
0FFFF316 to 0FFFF016 ID5
Watchdog timer vector
0FFFF716 to 0FFFF416 ID6
DBC vector
0FFFFB16 to 0FFFF816 ID7
NMI vector
0FFFFF16 to 0FFFFC16 ^{ROMCP Reset vector}
Figure 17.3 Address for ID Code Stored
Rev.2.10 Oct 25, 2006 Page 283 of 326
REJ03B0152-0210
4 bytes