M306H7MG-XXXFP Datasheet, PDF (143/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
11. Multi-master I²C-BUS Interface
The multi-master I²C-BUS interface have each dedicated circuit and operate independently.
The multi-master I²C-BUS interface is a serial communications circuit, conforming to the Philips I²C-BUS data
transfer format. This interface i, offering both arbitration lost detection and a synchronous functions, is useful for the
multi-master serial communications.
Table 11.1 shows multi-master I²C-BUS interface functions.
This multi-master I²C-BUS interface consists of I²C address register, I²C data shift register, I²C clock control register,
I²C control register, I²C status register, I²C transmit buffer register and the other control circuits.
Table 11.1 Clock Generation Circuit Specifications
Format
Item
Communication mode
Function
In conformity with Philips I²C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS standard:
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (BCLK = 16 MHz)
Power supply voltage on bus line (SCL3/SDA3) : VCC1
Note. ^{Our company doesn't assume the responsibility of the patent of the third party who originates in the use of the}
function to control the connection of I²C-BUS interface and ports (SCL3, SDA3) and other infringements of right.
Rev.2.10 Oct 25, 2006 Page 143 of 326
REJ03B0152-0210