M306H7MG-XXXFP Datasheet, PDF (104/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Table 10.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 10.3 shows
pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 10.4 lists
the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi
operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output
is selected, this pin is in a high-impedance state.)
Table 10.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
TxDi (i = 0 to 2) _{Serial data output}
(P63, P67, P70)
RxDi
Serial data input
(P62, P66, P71)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
Method of selection
(Outputs dummy data when performing reception only)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
UiMR register’s CKDIR bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
I/O port
UiC0 register’s CRD bit=1
Table 10.4 P64 Pin Functions
Pin function
P64
CTS1
RTS1
CTS0(Note1)
CLKS1
U1C0 register
CRD CRS
1
0
0
0
1
0
0
Bit set value
UCON register
RCSP CLKMD1 CLKMD0
0
0
0
0
0
0
1
0
1(Note 2)
1
PD6 register
PD6_4
Input: 0, Output: 1
0
0
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
Rev.2.10 Oct 25, 2006 Page 104 of 326
REJ03B0152-0210