M306H7MG-XXXFP Datasheet, PDF (155/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
• Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified,
so that a START condition and a STOP condition generated by the master are received, and data communication
is performed in synchronization with the clock generated by the master.
When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also
the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function
(See note).
• At reset
Note: The START condition duplication prevention function disables the following: the START condition
generation; bit counter reset, and SCL output with the generation. This bit is valid from setting of BB flag
to the completion of 1-byte transmission/reception (occurrence of transmission/ reception interrupt
request) <IICRQ>.
I²C status register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S1
Address
02E216
When reset
0001000?2
Bit Symbol
Bit name
LRB
Last receive bit
Function
RW
0 : Last bit = “0”
1 : Last bit = “1”
RO
(See note 1)
AD0
General call detecting 0 : No general call detected
RO
flag
1 : General call detected (See note 1)
AAS
Slave address comparison 0 : Address mismatch
flag
1 : Address match
RO
(See note 1)
AL
Arbitration lost detecting 0 : Not detected
flag
1 : Detected
RO
(See note 1)
PIN
I²C-BUS interface
0 : Interrupt request issued
RW
interrupt request bit
1 : No interrupt request issued (See note 2)
BB
Bus busy flag
0 : Bus free
1 : Bus busy
RO
(See note 1)
TRX
Communication mode b7b6
RW
specification bits
0 0 : Slave receive mode
MST
0 1 : Slave transmit mode
1 0 : Master receive mode
1 1 : Master transmit mode
Notes 1: These bits and flags can be read out, but cannot be written.
2: This bit can be written only “1.”
Figure 11.8 I²C status register
SCL
PIN
IICIRQ
Figure 11.9 Interrupt request signal generation timing
Rev.2.10 Oct 25, 2006 Page 155 of 326
REJ03B0152-0210