M306H7MG-XXXFP Datasheet, PDF (157/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(9) START/STOP condition detect conditions
The START/STOP condition detect conditions are shown in Figure 11.12 and Table 11.3.
Only when the 3 conditions of Table 11.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal <IICRQ> is
generated to the CPU.
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Setup
time
Hold
time
Setup
time
Hold
time
Figure 11.12 START condition/STOP condition detect timing diagram
Table 11.3 START condition/STOP condition detect conditions
Standard Clock Mode
6.5 µs < SCL release time
3.25 µs < Setup time
3.25 µs < Hold time
High-speed Clock Mode
1.0 µs < SCL release time
0.5 µs < Setup time
0.5 µs < Hold time
Rev.2.10 Oct 25, 2006 Page 157 of 326
REJ03B0152-0210