M306H7MG-XXXFP Datasheet, PDF (241/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
(3) Register related to Slicer
The relation between V, H signal, and the register related to slicer is shown in Figure. 14.13 and Figure. 14.14.
V after
SYNC separation
VPS_VP 0 to 8 (address 2916)
Setting the slice start line
After V input
The first line The second line
•••
The nth line The (n+1)th line The (n+17)th line
H after
SYNC separation
Figure 14.13 Register related to slicer (1)
After slice start
The 0th line The 1th line
On the odd field
LN0_OD1
LN0_OD0
On the even field
LN0_EV1
LN0_EV0
On the odd field
LN1_OD1
LN1_OD0
On the even field
LN1_EV1
LN1_EV0
The 17th line
On the odd field
LN17_OD1
LN17_OD0
On the even field
LN17_EV1
LN17_EV0
•••
Selection of a state register (addresses 00 to 0516)
(18 lines)
Clock
SELVCO, DIVS0 to 1
GETPEEK2
(Addresses 06, 0D, 1416) (Addresses 0A, 11, 1816)
Selection of the clock for slice
HOGO2(Addresses 09, 10, 1716)
Selection of the clock for
data acquisition
Selection of the clock
compensation after
a peak detection
period end
GET_HP0 to 1
(Addresses 0A, 11, 1816)
Phase adjustment
Clock run-in
Framing code
Data
H after
sync separation
SLSLVL0 to 1(Addresses 09, 10, 1716)
Slice level measurement period selection
Fixed
6 cycles
GETPEEK3
(Addresses 0A, 11, 1816)
A mountain and valley
detection selection
FLC0 to 15
(Addresses 07, 0C, 1316)
Framing code selection
CHK_FLC0 to 15
(Addresses 08, 0D, 1416)
Framing code check selection
BIFON(Addresses 07, 0C, 1316)
Data formal selection
SLS_HP0 to 7(Addresses 0A, 11, 1816)
Setting slice check start position
Fixed
Figure 14.14 Register related to slicer (2)
Rev.2.10 Oct 25, 2006 Page 241 of 326
REJ03B0152-0210