M306H7MG-XXXFP Datasheet, PDF (218/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
25. Address 2616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
DIVP_CK0
DIVP_CK1
DIVP_CK2
DIVP_CK3
DIVP_CK4
DIVP_CK5
DIVP_CK6
Bit name
Function
RW
The clock division value
The divided clock used for the phase
selection bit for phase
comparison with a PDC clock is set up.
comparison with a PDC clock
( ) ffSC = fDIVP ×
7
Σ
n
2
DIVS_CKn
+
2
n=0
fDIVP: The slice clock frequency
for PDC (please refer to
DIV_PDCS0 to 2 and
DIV_PDC0 to 4
(address 2216).)
When teletext (PDC) data is acquired
DIVP_CK7 to 0 = (00001110)2
When EPG-J is acquired
DIVP_CK7 to 0 = (00001001)2
DIVP_CK7
DIVV_CK0
DIVV_CK1
DIVV_CK2
The clock division value
The divided clock used for the phase
selection bit for phase
comparison with a VPS clock is set up.
comparison with a VPS clock
( ) ^{7 n}
ffSC = fDIVV × Σ 2 DIVV_CKn + 2
n=0
DIVV_CK3
DIVV_CK4
DIVV_CK5
DIVV_CK6
fDIVV : The slice clock frequency
for VPS (refer to
DIV_VPSS0 to 2 and
DIV_VPS0 to 4
(address 2316).)
When VPS is acquired
DIVV_CK7 to 0 = (00001110)2
When CC, CC2X and ID-1 are acquired
DIVV_CK7 to 0 = (01010011)2
DIVV_CK7
Rev.2.10 Oct 25, 2006 Page 218 of 326
REJ03B0152-0210