M306H7MG-XXXFP Datasheet, PDF (29/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Peripheral clock select register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 000 00
Symbol
PCLKR
Address
025E16
When reset
00000011 2
Bit symbol
Bit name
Function
RW
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A and B
0 : f2
1 : f1
RW
PCLK1 ^{SI/O clock select bit}
0 : f2SIO
(Clock source for UART0 _{1 : f1SIO}
RW
to UART2, SI/O3, SI/O4)
Reserved bit
(b7-b2)
Must set to “0”
RW
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 00 0
Symbol
PM2
Address
001E16
After reset
XXX000002
Bit symbol
Bit name
Function
RW
Reserved bit
(b0)
Must set to “0”
RW
PM21
System clock protective _{0 : Clock is protected by PRCR}
bit
register
RW
(Note 2, Note 3) _{1 : Clock modification disabled}
(b4-b2)
Reserved bit
Must set to “0”
RW
(b7-b5)
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 3: If the PM21 bit is set to “1,” writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
Figure 4.4 PCLKR Register and PM2 Register
Rev.2.10 Oct 25, 2006 Page 29 of 326
REJ03B0152-0210