M306H7MG-XXXFP Datasheet, PDF (158/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(10) Address data communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing
format. The respective address communication formats is described below.
• 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I²C control register to “0.” The first 7-bit
address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I²C
address register. At the time of this comparison, address comparison of the RBW bit of the I²C address register is
not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 11.13 (1)
and (2).
• 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I²C control register to “1.” An address
comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address
stored in the I²C address register. At the time of this comparison, an address comparison between the RBW bit of
the I²C address register and the R/W bit which is the last bit of the address data transmitted from the master is
made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the
direction of communication for control data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I²C status register is set to “1.”
After the second-byte address data is stored into the I²C data shift register, make an address comparison between
the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave
address, set the RBW bit of the I²C address register to “1” by software. This processing can match the 7-bit slave
address and R/W data, which are received after a RESTART condition is detected, with the value of the I²C
address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure
11.13, (3) and (4).
Rev.2.10 Oct 25, 2006 Page 158 of 326
REJ03B0152-0210