M306H7MG-XXXFP Datasheet, PDF (284/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
17. FLASH MEMORY VERSION
17.5 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without
having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 17.1 can be rewritten and the boot ROM area
cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on each block in the
user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write
1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes.
Table 17.3 EW0 Mode and EW1 Mode
Item
EW0 mode
EW1 mode
Operation mode
• Single chip mode
Single chip mode
• Boot mode
Areas in which a
• User ROM area
User ROM area
rewrite control
• Boot ROM area
program can be located
Areas in which a
Must be transferred to any area other Can be executed directly in the user
rewrite control
than the flash memory (RAM)
ROM area
program can be executed before being executed (Note 2)
Areas which can be
User ROM area
User ROM area
rewritten
However, this does not include the area
in which a rewrite control program
exists
Software command
None
• Program, Block Erase command
limitations
Cannot be executed on any block in
which a rewrite control program exists
• Read Status Register command
Cannot be executed
Modes after Program or Read Status Register mode
Read Array mode
Erase
CPU status during Auto Operating
Hold state (I/O ports retain the state in
Write and Auto Erase
which they were before the command
was executed)^{(Note 1)}
Flash memory status • Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
detection
FMR06, and FMR07 bits in a
FMR06, and FMR07 bits in a program
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
_______
Note 1: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, bit 0 and bit 3 in the PM1 register are set to "1". The rewrite control
program can only be executed in the internal RAM.
Rev.2.10 Oct 25, 2006 Page 284 of 326
REJ03B0152-0210