M306H7MG-XXXFP Datasheet, PDF (146/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(2) I²C data shift register, I²C transmit buffer register
The I²C data shift register is an 8-bit shift register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with
the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When
data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit
data is input, the data of this register are shifted one bit to the left.
The I²C data shift register is in a write enable status only when the ESO bit of the I²C control register is “1.” The
bit counter is reset by a write instruction to the I²C data shift register. When both the ESO bit and the MST bit of
the I²C status register are “1,” the SCL is output by a write instruction to the I²C data shift register. Reading data
from the I²C data shift register is always enabled regardless of the ESO bit value.
The I²C transmit buffer register is a register to store transmit data (slave address) to the I²C data shift register
before RESTART condition generation. That is, in master, transmit data written to the I²C transmit buffer register
is written to the I²C data shift register simultaneously. However, the SCL is not output. The I²C transmit buffer
register can be written only when the ESO bit is “1,” reading data from the I²C transmit buffer register is disabled
regardless of the ESO bit value.
Notes 1: To write data into the I²C data shift register or the I²C transmit buffer register after the MST bit value
changes from “1” to “0” (slave mode), keep an interval of 20 BCLK or more.
2: To generate START/RESTART condition after the I²C data shift register or the I²C transmit buffer
register is written, keep an interval of 4 BCLK or more.
Rev.2.10 Oct 25, 2006 Page 146 of 326
REJ03B0152-0210