M306H7MG-XXXFP Datasheet, PDF (69/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
8. DMAC
8.2 Number of DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 8.2 shows the number of DMA
transfer cycles. Table 8.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 8.2 Number of DMA Transfer Cycles
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Bus width
Single-chip mode
Access address
No. of read No. of write
cycles
cycles
16-bit
Even
1
1
(BYTE= “L”)
Odd
1
1
16-bit
Even
1
1
(BYTE = “L”)
Odd
2
2
Table 8.3 Coefficient j, k
Internal area
Internal ROM, RAM SFR
No wait With wait
j1
2
2
k1
2
2
Rev.2.10 Oct 25, 2006 Page 69 of 326
REJ03B0152-0210