M306H7MG-XXXFP Datasheet, PDF (34/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
4.4 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred
to as normal operation mode here.
4.4.1 Normal Operation Mode
Normal operation mode is further classified into four modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and
the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The
higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the
smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must
be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait time in a
program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count
source for timers A and B.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function
clock.
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the
CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8 mode).
In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by
8) mode is to be selected when the main clock is operated next.
Rev.2.10 Oct 25, 2006 Page 34 of 326
REJ03B0152-0210