PIC18F97J60_11 Datasheet, PDF (96/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on Details on
POR, BOR Page:
EHT7
Hash Table Register Byte 7
0000 0000 74, 259
EHT6
Hash Table Register Byte 6
0000 0000 74, 259
EHT5
Hash Table Register Byte 5
0000 0000 74, 259
EHT4
Hash Table Register Byte 4
0000 0000 74, 259
EHT3
Hash Table Register Byte 3
0000 0000 74, 259
EHT2
Hash Table Register Byte 2
0000 0000 74, 259
EHT1
Hash Table Register Byte 1
0000 0000 74, 259
EHT0
Hash Table Register Byte 0
0000 0000 74, 259
MIRDH
MII Read Data Register High Byte
0000 0000 74, 232
MIRDL
MII Read Data Register Low Byte
0000 0000 74, 232
MIWRH
MII Write Data Register High Byte
0000 0000 74, 232
MIWRL
MII Write Data Register Low Byte
0000 0000 74, 232
MIREGADR
—
—
—
MII Address Register
---0 0000 74, 232
MICMD
—
—
—
—
—
—
MIISCAN
MIIRD ---- --00 74, 231
MAMXFLH Maximum Frame Length Register High Byte
0000 0110 74, 245
MAMXFLL Maximum Frame Length Register Low Byte
0000 0000 74, 245
MAIPGH
—
MAC Non Back-to-Back Inter-Packet Gap Register High Byte
-000 0000 75, 245
MAIPGL
—
MAC Non Back-to-Back Inter-Packet Gap Register Low Byte
-000 0000 75, 245
MABBIPG
—
BBIPG6
BBIPG5
BBIPG4
BBIPG3
BBIPG2
BBIPG1
BBIPG0 -000 0000 75, 246
MACON4
—
DEFER
r
r
—
—
r
r
-000 --00 75, 231
MACON3
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 75, 230
MACON1
—
—
—
r
TXPAUS RXPAUS PASSALL MARXEN ---0 0000 75, 229
EPAUSH
Pause Timer Value Register High Byte
0001 0000 75, 258
EPAUSL
Pause Timer Value Register Low Byte
0000 0000 75, 258
EFLOCON
—
—
—
—
—
r
FCEN1
FCEN0 ---- -000 75, 258
MISTAT
—
—
—
—
r
NVALID
SCAN
BUSY ---- 0000 75, 232
MAADR2 MAC Address Register Byte 2 (MAADR<39:32>), OUI Byte 2
0000 0000 75, 245
MAADR1 MAC Address Register Byte 1 (MAADR<47:40>), OUI Byte 1
0000 0000 75, 245
MAADR4 MAC Address Register Byte 4 (MAADR<23:16>)
0000 0000 75, 245
MAADR3 MAC Address Register Byte 3 (MAADR<31:24>), OUI Byte 3
0000 0000 75, 245
MAADR6 MAC Address Register Byte 6 (MAADR<7:0>)
0000 0000 75, 245
MAADR5 MAC Address Register Byte 5 (MAADR<15:8>)
0000 0000 75, 245
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
DS39762F-page 96
 2011 Microchip Technology Inc.