PIC18F97J60_11 Datasheet, PDF (165/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-17: PORTH FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16
RH0
0
O DIG LATH<0> data output.
1
I
ST PORTH<0> data input.
A16⁽¹⁾
x
O DIG External memory interface, Address Line 16. Takes priority over port data.
RH1/A17
RH1
0
O DIG LATH<1> data output.
1
I
ST PORTH<1> data input.
A17⁽¹⁾
x
O DIG External memory interface, Address Line 17. Takes priority over port data.
RH2/A18
RH2
0
O DIG LATH<2> data output.
1
I
ST PORTH<2> data input.
A18⁽¹⁾
x
O DIG External memory interface, Address Line 18. Takes priority over port data.
RH3/A19
RH3
0
O DIG LATH<3> data output.
1
I
ST PORTH<3> data input.
A19⁽¹⁾
x
O DIG External memory interface, Address Line 19. Takes priority over port data.
RH4/AN12/P3C RH4
0
O DIG LATH<4> data output.
1
I
ST PORTH<4> data input.
AN12
I ANA A/D Input Channel 12. Default input configuration on POR; does not affect
digital output.
P3C⁽²⁾
0
O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH5/AN13/P3B RH5
0
O DIG LATH<5> data output.
1
I
ST PORTH<5> data input.
AN13
I ANA A/D Input Channel 13. Default input configuration on POR; does not affect
digital output.
P3B⁽²⁾
0
O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH6/AN14/P1C RH6
0
O DIG LATH<6> data output.
1
I
ST PORTH<6> data input.
AN14
I ANA A/D Input Channel 14. Default input configuration on POR; does not affect
digital output.
P1C⁽²⁾
0
O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH7/AN15/P1B RH7
0
O DIG LATH<7> data output.
1
I
ST PORTH<7> data input.
AN15
I ANA A/D Input Channel 15. Default input configuration on POR; does not affect
digital output.
P1B⁽²⁾
0
O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Unimplemented on 80-pin devices.
Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared (80-pin and 100-pin
devices only). Default assignments are PORTE<6:3>.
TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTH
LATH
TRISH
RH7
LATH7
TRISH7
RH6
LATH6
TRISH6
RH5
LATH5
TRISH5
RH4
LATH4
TRISH4
RH3
LATH3
TRISH3
RH2
LATH2
TRISH2
RH1
LATH1
TRISH1
Bit 0
RH0
LATH0
TRISH0
Reset
Values
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 2011 Microchip Technology Inc.
DS39762F-page 165