PIC18F97J60_11 Datasheet, PDF (203/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

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18.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCPx modules and offers up to four out-
puts, designated PxA through PxD. Users are also able
to select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the PxM<1:0> and CCPxM<3:0>
bits of the CCPxCON register (CCPxCON<7:6> and
<3:0>, respectively).
For the sake of clarity, Enhanced PWM mode operation
is described generically throughout this section with
respect to ECCP1 and TMR2 modules. Control register
names are presented in terms of ECCP1. All three
Enhanced modules, as well as the two timer resources,
can be used interchangeably and function identically.
TMR2 or TMR4 can be selected for PWM operation by
selecting the proper bits in T3CON.
Figure 18-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
ECCP1 Dead-Band Delay register, ECCP1DEL, which
is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead, offset by
one full instruction cycle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
18.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 18-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The ECCP1 pin is set (if PWM duty cycle = 0%,
the ECCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
FIGURE 18-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Duty Cycle Registers
CCPR1L
CCP1CON<5:4> _P1M1<1:0>
2
CCP1M<3:0>
4
ECCP1/P1A
TRISx<x>
CCPR1H (Slave)
Comparator
TMR2
(Note 1)
R
Q
S
P1B
Output
Controller
P1C
TRISx<x>
TRISx<x>
Comparator
PR2
Clear Timer,
set ECCP1 pin and
latch D.C.
P1D
ECCP1DEL
TRISx<x>
ECCP1/P1A
P1B
P1C
P1D
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
 2011 Microchip Technology Inc.
DS39762F-page 203