PIC18F97J60_11 Datasheet, PDF (92/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on Details on
POR, BOR Page:
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 70, 97
TMR0H
Timer0 Register High Byte
0000 0000 70, 171
TMR0L
Timer0 Register Low Byte
xxxx xxxx 70, 171
T0CON
OSCCON
TMR0ON
IDLEN
T08BIT
—
T0CS
—
T0SE
—
PSA
OSTS⁽³⁾
T0PS2
—
T0PS1
SCS1
T0PS0
SCS0
1111 1111 70, 171
0--- q-00 70, 53
ECON1
TXRST
RXRST
DMAST CSUMEN TXRTS
RXEN
—
—
0000 00-- 70, 227
WDTCON
—
—
—
—
—
—
—
SWDTEN --- ---0 70, 368
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR 0-q1 1100 70, 64, 143
TMR1H
Timer1 Register High Byte
xxxx xxxx 70, 175
TMR1L
Timer1 Register Low Byte
xxxx xxxx 70, 175
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 70, 175
TMR2
Timer2 Register
0000 0000 70, 180
PR2
Timer2 Period Register
1111 1111 70, 180
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 180
SSP1BUF
SSP1ADD
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I²C™ Slave mode), MSSP1 Baud Rate Reload Register (I²C Master mode)
xxxx xxxx 70, 279
0000 0000 70, 279
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 70, 270,
280
SSP1CON1 WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 70, 271,
281
SSP1CON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
ACKSTAT ADMSK5⁽⁴⁾ ADMSK4⁽⁴⁾ ADMSK3⁽⁴⁾ ADMSK2⁽⁴⁾ ADMSK1⁽⁴⁾
SEN
SEN
0000 0000 70, 282
ADRESH A/D Result Register High Byte
xxxx xxxx 70, 347
ADRESL
A/D Result Register Low Byte
xxxx xxxx 70, 347
ADCON0
ADCAL
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON 0-00 0000 70, 339
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 --00 0000 70, 340
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 70, 341
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 70, 193
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 70, 193
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 70, 198
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 70, 193
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 70, 193
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 70, 198
CCPR3H
Capture/Compare/PWM Register 3 High Byte
xxxx xxxx 70, 193
CCPR3L
Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx 70, 193
CCP3CON
P3M1
P3M0
DC3B1
DC3B0
CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 70, 198
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70, 212
CVRCON
CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 70, 355
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0111 70, 349
TMR3H
Timer3 Register High Byte
xxxx xxxx 70, 183
TMR3L
Timer3 Register Low Byte
xxxx xxxx 70, 183
Legend: x = unknown; u = unchanged; - = unimplemented, read as ‘0’; q = value depends on condition; r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
DS39762F-page 92
 2011 Microchip Technology Inc.