PIC18F97J60_11 Datasheet, PDF (445/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
1
2
3
4
5
Note 1:
FOSC
External CLKI Frequency⁽¹⁾
DC
41.6667 MHz EC Oscillator mode
Oscillator Frequency⁽¹⁾
6
25
MHz HS Oscillator mode
TOSC
External CLKI Period⁽¹⁾
24
—
ns EC Oscillator mode
Oscillator Period⁽¹⁾
40
167
ns HS Oscillator mode
TCY
Instruction Cycle Time⁽¹⁾
96
—
ns TCY = 4/FOSC, Industrial
TOSL,
External Clock in (OSC1)
10
TOSH
High or Low Time
—
ns EC Oscillator mode
TOSR, External Clock in (OSC1)
—
TOSF
Rise or Fall Time
7.5
ns EC Oscillator mode
Clock Frequency Tolerance
—
±50
ppm Ethernet module enabled
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
 2011 Microchip Technology Inc.
DS39762F-page 445