PIC18F97J60_11 Datasheet, PDF (147/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-3: PORTA FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/LEDA/AN0
RA0
0
O
DIG LATA<0> data output; not affected by analog input.
1
I
TTL PORTA<0> data input; disabled when analog input is enabled.
LEDA
0
O
DIG Ethernet LEDA output; takes priority over digital data.
AN0
1
I
ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/LEDB/AN1
RA1
0
O
DIG LATA<1> data output; not affected by analog input.
1
I
TTL PORTA<1> data input; disabled when analog input is enabled.
LEDB
0
O
DIG Ethernet LEDB output; takes priority over digital data.
AN1
1
I
ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/VREF-
RA2
0
O
DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output is enabled.
1
I
TTL PORTA<2> data input. Disabled when analog functions are enabled;
disabled when CVREF output is enabled.
AN2
1
I
ANA A/D Input Channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF-
1
I
ANA A/D and comparator low reference voltage input.
RA3/AN3/VREF+ RA3
0
O
DIG LATA<3> data output; not affected by analog input.
1
I
TTL PORTA<3> data input; disabled when analog input is enabled.
AN3
1
I
ANA A/D Input Channel 3. Default input configuration on POR.
VREF+
1
I
ANA A/D high reference voltage input.
RA4/T0CKI
RA4
0
O
DIG LATA<4> data output.
1
I
ST PORTA<4> data input; default configuration on POR.
T0CKI
x
I
ST Timer0 clock input.
RA5/AN4
RA5
0
O
DIG LATA<5> data output; not affected by analog input.
1
I
TTL PORTA<5> data input; disabled when analog input is enabled.
AN4
1
I
ANA A/D Input Channel 4. Default configuration on POR.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTA
RJPU⁽¹⁾
—
RA5
RA4
RA3
RA2
RA1
LATA
RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Implemented in 80-pin and 100-pin devices only.
Bit 0
RA0
LATA0
TRISA0
PCFG0
Reset
Values on
Page:
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 2011 Microchip Technology Inc.
DS39762F-page 147