PIC18F97J60_11 Datasheet, PDF (219/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.1.4
MAGNETICS, TERMINATION AND
OTHER EXTERNAL COMPONENTS
To complete the Ethernet interface, the Ethernet
module requires several standard components to be
installed externally. These components should be
connected, as shown in Figure 19-2.
The internal analog circuitry in the PHY module requires
that an external resistor (2.26 k) be attached from
RBIAS to ground. The resistor influences the TPOUT+/-
signal amplitude. It should be placed as close as possible
to the chip with no immediately adjacent signal traces to
prevent noise capacitively coupling into the pin and
affecting the transmit behavior. It is recommended that
the resistor be a surface mount type.
On the TPIN+/TPIN- and TPOUT+/TPOUT- pins,
1:1 center-tapped pulse transformers, rated for Ethernet
operations (10/100 or 10/100/1000), are required. When
the Ethernet module is enabled, current is continually
sunk through both TPOUT pins. When the PHY is
actively transmitting, a differential voltage is created on
the Ethernet cable by varying the relative current sunk
by TPOUT+ compared to TPOUT-.
A common-mode choke on the PHY side of the interface
(i.e., between the microcontrollers’s TPOUT pins and
the Ethernet transformer) is not recommend. If a
common-mode choke is used to reduce EMI emissions,
it should be placed between the Ethernet transformer
and Pins 1 and 2, of the RJ-45 connector. Many Ethernet
transformer modules include common-mode chokes
inside the same device package. The transformers
should have at least the isolation rating specified in
Table 28-28 to protect against static voltages and meet
IEEE 802.3 isolation requirements (see Section 28.5
“Ethernet Specifications and Requirements” for
specific transformer requirements). Both transmit and
receive interfaces additionally require two resistors and
a capacitor to properly terminate the transmission line,
minimizing signal reflections.
All power supply pins must be externally connected to
the same power source. Similarly, all ground refer-
ences must be externally connected to the same
ground node. Each VDD and VSS pin pair should have
a 0.1 F ceramic bypass capacitor placed as close to
the pins as possible.
Since relatively high currents are necessary to operate
the twisted-pair interface, all wires should be kept as
short as possible. Reasonable wire widths should be
used on power wires to reduce resistive loss. If the
differential data lines cannot be kept short, they should
be routed in such a way as to have a 100 characteristic
impedance.
FIGURE 19-2:
EXTERNAL COMPONENTS REQUIRED FOR ETHERNET OPERATION
C1⁽³⁾
25 MHz
C2⁽³⁾
PIC18FXXJ6X
TPOUT+
120⁽¹⁾
3.3V
56pF⁽¹⁾
±5%
49.9, 1%
OSC1
OSC2
TPOUT-
120⁽¹⁾
TPIN+ _56pF(1)
±5%
49.9, 1%
49.9, 1%
TPIN-
49.9, 1%
0.1 F⁽¹⁾
0.1 F
1:1 CT
1:1 CT
LEDA
LEDB RBIAS
2.26 k, 1%
CMC⁽²⁾
CMC⁽²⁾
1
RJ-45
1
2
3
4
5
6
7
8
1 nF, 2 kV⁽¹⁾
Note 1:
2:
3:
4:
These components are installed for EMI reduction purposes. See Section 19.1.5 for more information.
Recommended insertion point for Common-Mode Chokes (CMCs) if required for EMI reduction.
See Section 3.3 “Crystal Oscillator/Ceramic Resonators (HS Modes)” for recommended values.
Power over Ethernet applications require capacitors in series with these resistors.
 2011 Microchip Technology Inc.
DS39762F-page 219