PIC18F97J60_11 Datasheet, PDF (235/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 19-9: PHCON1: PHY CONTROL REGISTER 1
R/W-0
R/W-0
U-0
r
r
—
bit 15
U-0
R/W-0
—
r
R/W-0
r
U-0
R/W-0
—
PDPXMD
bit 8
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
r
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-12
bit 11-10
bit 9
bit 8
bit 7
bit 6-0
Reserved: Write as ‘0’
Unimplemented: Read as ‘0’
Reserved: Write as ‘0’
Unimplemented: Read as ‘0’
PDPXMD: PHY Duplex Mode bit
1 = PHY operates in Full-Duplex mode; application must also set FULDPX (MACON3<0>)
0 = PHY operates in Half-Duplex mode, application must also clear FULDP
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
REGISTER 19-10: PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
U-0
U-0
U-0
R-1
R-1
U-0
U-0
—
—
—
r
r
—
—
bit 15
U-0
—
bit 8
U-0
U-0
U-0
U-0
U-0
R/LL-0
R/LH-0
U-0
—
—
—
—
—
LLSTAT
r
—
bit 7
bit 0
Legend:
R = Read-only bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
R/L = Read-Only Latch bit
r = Reserved bit
U = Unimplemented bit, read as ‘0’
LL = Latches Low bit
LH = Latches High bit
bit 15-13
bit 12-11
bit 10-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Read as ‘1’
Unimplemented: Read as ‘0’
LLSTAT: PHY Latching Link Status bit
1 = Link is up and has been up continously since PHSTAT1 was last read
0 = Link is down or was down for a period since PHSTAT1 was last read
Reserved: Ignore on read
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
DS39762F-page 235