PIC18F97J60_11 Datasheet, PDF (479/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
Memory Maps
Ethernet Special Function Registers ................. 90
PIC18F97J60 Family ......................................... 87
Special Function Registers ................................ 89
Special Function Registers ........................................ 89
DAW ................................................................................. 394
DC Characteristics ........................................................... 439
Power-Down and Supply Current ............................ 432
Supply Voltage ......................................................... 431
DCFSNZ .......................................................................... 395
DECF ............................................................................... 394
DECFSZ ........................................................................... 395
Default System Clock ......................................................... 54
Development Support ...................................................... 425
Device Differences ........................................................... 476
Device Overview ................................................................ 11
Details on Individual Family Members ....................... 12
Features (100-Pin Devices) ....................................... 14
Features (64-Pin Devices) ......................................... 13
Features (80-Pin Devices) ......................................... 13
Direct Addressing ............................................................... 99
E
ECCP2
Pin Assignment ........................................................ 190
Effect on Standard PIC Instructions ................................. 422
Electrical Characteristics .................................................. 429
Requirements for Ethernet Transceiver
External Magnetics .......................................... 463
Enhanced Capture/Compare/PWM (ECCP) .................... 197
Capture and Compare Modes .................................. 202
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and Program
Memory Mode .................................................. 199
ECCP2 Outputs and Program Memory Modes ........ 199
Enhanced PWM Mode ............................................. 203
Outputs and Configuration ....................................... 199
Pin Configurations for ECCP1 ................................. 200
Pin Configurations for ECCP2 ................................. 200
Pin Configurations for ECCP3 ................................. 201
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 202
Timer Resources ...................................................... 199
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 199
Enhanced Capture/Compare/PWM (ECCPx)
Associated Registers ............................................... 215
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG pin .................................................................... 369
Equations
16 x 16 Signed Multiplication Algorithm ................... 128
16 x 16 Unsigned Multiplication Algorithm ............... 128
A/D Acquisition Time ................................................ 344
A/D Minimum Charging Time ................................... 344
Calculating Baud Rate Error .................................... 320
Calculating the A/D Minimum Required
Acquisition Time .............................................. 344
Random Access Address Calculation ...................... 253
Receive Buffer Free Space Calculation ................... 254
Errata ................................................................................... 9
Ethernet Module .............................................................. 217
Associated Registers, Direct Memory Access
Controller ......................................................... 266
Associated Registers, Flow Control ......................... 258
Associated Registers, Reception ............................. 255
Associated Registers, Transmission ....................... 255
Automatic RX Polarity Detection, Correction ........... 220
Buffer and Buffer Pointers ....................................... 223
Buffer Arbiter ................................................... 226
DMA Access .................................................... 226
Receive Buffer ................................................. 225
Transmit Buffer ................................................ 226
Buffer and Register Spaces ..................................... 222
Buffer Organization .................................................. 224
CRC ......................................................................... 248
Direct Memory Access (DMA) Controller ................. 265
Direct Memory Access Controller
Checksum Calculations ................................... 266
Copying Memory ............................................. 265
Disabling .................................................................. 246
Duplex Mode Configuration and Negotiation ........... 256
EMI Emissions Considerations ................................ 220
Ethernet and Microcontroller Memory
Relationship ..................................................... 222
Ethernet Control Registers ...................................... 227
Flow Control ............................................................ 257
Initializing ................................................................. 245
Interrupts ................................................................. 239
Interrupts and Wake-on-LAN ................................... 244
LED Configuration ................................................... 218
MAC and MII Registers ........................................... 229
MAC Initialization Settings ....................................... 245
Magnetics, Termination and Other External
Components .................................................... 219
Memory Maps .......................................................... 234
Oscillator Requirements .......................................... 218
Packet Format ......................................................... 247
Per-Packet Control Bytes ........................................ 249
PHSTAT Registers .................................................. 232
PHY Initialization Settings ....................................... 246
PHY Registers ......................................................... 232
PHY Start-up Timer ................................................. 218
Reading from a PHY Register ................................. 233
Receive Filters ......................................................... 259
Broadcast ........................................................ 259
Hash Table ...................................................... 259
Magic Packet ................................................... 259
Multicast .......................................................... 259
Pattern Match .................................................. 259
Unicast ............................................................ 259
Resets ..................................................................... 267
Microcontroller Reset ....................................... 267
Receive Only ................................................... 267
Transmit Only .................................................. 267
Signal and Power Interfaces .................................... 218
Special Function Registers (SFRs) ......................... 227
 2011 Microchip Technology Inc.
DS39762F-page 479