PIC18F97J60_11 Datasheet, PDF (266/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

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19.9.2 CHECKSUM CALCULATIONS
The checksum calculation logic treats the source data
as a series of 16-bit big-endian integers. If the source
range contains an odd number of bytes, a padding byte
of 00h is effectively added to the end of the series for
purposes of calculating the checksum.
The calculated checksum is the 16-bit, one’s
complement of the one’s complement sum of all 16-bit
integers. For example, if the bytes included in the
checksum were {89h, ABh, CDh}, the checksum would
begin by computing: 89ABh + CD00h. A carry out of the
16th bit would occur in the example, so in 16-bit one’s
complement arithmetic, it would be added back to the
first bit. The resulting value of 56ACh would finally be
complemented to achieve a checksum of A953h.
To calculate a checksum:
1. Set the EDMAST and EDMAND register pairs to
point to the first and last bytes of buffer data to
be included in the checksum. Care should be
taken when programming these pointers to
prevent a never-ending checksum calculation
due to receive buffer wrapping.
2. To generate an optional interrupt when the
checksum calculation is done, set the DMAIE
(EIE<5>) and ETHIE (PIE2<5>) bits and clear
the DMAIF (EIR<5>) bit.
3. Start the calculation by setting the CSUMEN
(ECON1<4>) and DMAST (ECON1<5>) bits.
When the checksum is finished being calculated, the
hardware will clear the DMAST bit, set the DMAIF bit
and an interrupt will be generated, if enabled. The DMA
Pointers will not be modified and no memory will be
written to. The EDMACSH and EDMACSL registers will
contain the calculated checksum. The application may
write this value into a packet, compare this value with
zero (to validate a received block of data containing a
checksum field in it), or compare it with some other
checksum, such as a pseudo header checksum used in
various protocols (TCP, UDP, etc.).
When operating the DMA in Checksum mode, it takes
one instruction cycle (TCY) for every byte included in
the checksum. As a result, if a checksum over
1446 bytes was performed, the DMA module would
require slightly more than 138.8 s to complete the
operation at 41.667 MHz.
At the same frequency, a small 20-byte header field
would take approximately 1.9 s plus DMA setup time
to calculate a sum. These estimated times assume that
the Ethernet receive hardware does not need memory
access bandwidth and the CPU does not issue any
reads or writes to the EDATA register while the DMA is
computing.
Like the DMA Copy mode, the checksum operation will
not start until the TXRTS bit (ECON1<3>) is clear. This
may considerably increase the checksum calculation
time if the application transmits a large packet and
immediately attempts to validate a checksum on a
received packet.
TABLE 19-10: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page
EIE
—
PKTIE DMAIE LINKIE
TXIE
—
TXERIE RXERIE
73
EIR
—
PKTIF DMAIF LINKIF
TXIF
—
TXERIF RXERIF
73
ECON1
TXRST RXRST DMAST CSUMEN TXRTS RXEN
—
—
70
ERXNDL
Receive End Register Low Byte (ERXND<7:0>)
73
ERXNDH
—
—
— Receive End Register High Byte (ERXND<12:8>)
73
EDMASTL DMA Start Register Low Byte (EDMAST<7:0>)
73
EDMASTH
—
—
— DMA Start Register High Byte (EDMAST<12:8>)
73
EDMANDL DMA End Register Low Byte (EDMAND<7:0>)
73
EDMANDH
—
—
— DMA End Register High Byte (EDMAND<12:8>)
73
EDMADSTL DMA Destination Register Low Byte (EDMADST<7:0>)
73
EDMADSTH
—
—
— DMA Destination Register High Byte (EDMADST<12:8>)
73
EDMACSL DMA Checksum Register Low Byte (EDMACS<7:0>)
73
EDMACSH DMA Checksum Register High Byte (EDMACS<15:8>)
73
Legend: — = unimplemented. Shaded cells are not used.
DS39762F-page 266
 2011 Microchip Technology Inc.