PIC18F97J60_11 Datasheet, PDF (168/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
11.11 Parallel Slave Port (PSP)
Note: The Parallel Slave Port is only implemented
on 100-pin devices.
PORTD can also function as an 8-bit wide, Parallel
Slave Port, or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. It is asynchronously
readable and writable by the external world through the
RD control input pin, RE0/AD8/RD/P2D and WR
control input pin, RE1/AD9//WR/P2C.
Note: The Parallel Slave Port is available only in
Microcontroller mode.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit, PSPMODE, enables port pin, RE0/AD8/RD/P2D, to
be the RD input, RE1/AD9//WR/P2C to be the WR
input and RE2/AD10//CS/P2B to be the CS (Chip
Select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 11-3 and Figure 11-4,
respectively.
FIGURE 11-2:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
Q
WR LATD
or PORTD
CK
Data Latch
Q
D
RD PORTD
EN^EN
TRIS Latch
RPDinx
TTL
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
DS39762F-page 168
 2011 Microchip Technology Inc.