PIC18F97J60_11 Datasheet, PDF (265/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

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19.9 Direct Memory Access Controller
The Ethernet module incorporates a dual purpose DMA
controller, which can be used to copy data between loca-
tions within the 8-Kbyte memory buffer. It can also be
used to calculate a 16-bit checksum which is compatible
with various industry standard communication protocols,
including TCP, UDP, IP, ICMP, etc.
The DMA is controlled using three pointers and several
status/control bits:
• EDMASTH:EDMASTL: Source Start Address
• EDMANDH:EDMANDL: Source End Address
• EDMADSTH:EDMADSTL: Destination Start
Address
• DMAST and CSUMEN (ECON1<5,4>): DMA
Start/Busy and Checksum Enable bits
• DMAIE and DMAIF (EIE<5> and EIR<5>): DMA
Interrupt Enable and Flag bits
The Source and End Pointers define what data will be
copied or checksumed. The Destination Pointer, used
only when copying data, defines where copied data will
be placed. All three pointers are with respect to the
8-Kbyte Ethernet memory and cannot be used to
access memory in the PIC^® microcontroller data
memory space.
When a DMA operation begins, the EDMAST register
pair is copied into an Internal Source Pointer. The DMA
will execute on one byte at a time and then increment the
Internal Source Pointer. However, if a byte is processed
and the Internal Source Pointer is equal to the Receive
Buffer End Pointer pair, ERXND, the Source Pointer will
not be incremented. Instead, the Internal Source Pointer
will be loaded with the Receive Buffer Start Pointer pair,
ERXST. In this way, the DMA will follow the circular FIFO
structure of the receive buffer and received packets can
be processed using one operation. The DMA operation
will end when the Internal Source Pointer matches the
EDMAND Pointers.
While any DMA operation is in progress, the DMA Point-
ers and the CSUMEN bit (ECON1<4>) should not be
modified. The DMA operation can be canceled at any
time by clearing the DMAST bit (ECON1<5>). No regis-
ters will change; however, some memory bytes may
already have been copied if a DMA copy was in progress.
Some operational requirements must always be kept in
mind when using the DMA. Failure to observe these
requirements may result in a loss of Ethernet buffer
data, or even complete failure of Ethernet operation:
• If the EDMAND Pointers cannot be reached
because of the receive buffer wrapping behavior,
the DMA operation will never end.
• By design, the DMA module cannot be used to
copy or calculate a checksum over only one byte
(EDMAST = EDMAND). An attempt to do so may
overwrite all memory in the buffer and never end.
• After termination of a DMA operation (DMAST is
cleared by hardware or firmware), the application
must not set DMAST again within 4 instruction
cycles.
• To ensure reliable operation, avoid having the
application access EDATA during a DMA copy
operation. EDATA may be safely accessed during
DMA checksum operations.
19.9.1 COPYING MEMORY
To copy memory within the buffer:
1. Program the EDMAST, EDMAND and EDMADST
register pairs with the appropriate start, end and
destination addresses. The EDMAST registers
should point to the first byte to copy from, the
EDMAND registers should point to the last byte to
copy and the EDMADST registers should point to
the first byte in the destination range. The destina-
tion range will always be linear, never wrapping at
any values except from 8191 to 0 (the 8-Kbyte
memory boundary). Extreme care should be
taken when calculating the End Pointer to prevent
a never ending DMA operation which would
overwrite the entire 8-Kbyte buffer.
2. If desired, set the DMAIE (EIE<5>) and ETHIE
(PIE2<5>) bits, and clear the DMAIF (EIR<5>)
flag bit to enable an interrupt at the end of the
copy process.
3. Clear the CSUMEN (ECON1<4>) bit.
4. Start the DMA copy by setting the DMAST
(ECON1<5>) bit.
If a transmit operation is in progress (TXRTS bit is set)
while the DMAST bit is set, the module will wait until the
transmit operation is complete before attempting to do
the DMA copy. This possible delay is required because
the DMA and transmission engine are unable to access
the buffer at the same time.
When the copy is complete, the DMA hardware will
clear the DMAST bit, set the DMAIF bit and generate
an interrupt (if enabled). The pointers and the
EDMACS registers will not be modified.
After the DMA module has been initialized and has
begun its copy, one instruction cycle (TCY) will be
required for each byte copied. However, if the Ethernet
receive hardware accumulates one byte of data, the
DMA will stall that cycle, yielding to the higher priority
operation. If a maximum size, 1518-byte packet was
copied while no other memory bandwidth was being
used, the DMA module would require slightly more than
145.7 s to complete at a core frequency of 41.667
MHz. The time required to copy a minimum size packet
of 64 bytes would be approximately 6.2 s (at
41.667 MHz), plus register configuration time.
 2011 Microchip Technology Inc.
DS39762F-page 265