PIC18F97J60_11 Datasheet, PDF (155/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 11-9: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/AD0/PSP0
(RD0/P1B)
RD0
0
O
DIG LATD<0> data output.
1
I
ST PORTD<0> data input; weak pull-up when RDPU bit is set.
AD0⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 0 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 0 input.⁽²⁾
PSP0⁽¹⁾
x
O
DIG PSP read output data (LATD<0>); takes priority over port data.
x
I
TTL PSP write data input.
P1B⁽³⁾
0
O
DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD1/AD1/PSP1 RD1
0
(RD1/ECCP3/
1
P3A)
AD1⁽¹⁾
x
O
DIG LATD<1> data output.
I
ST PORTD<1> data input; weak pull-up when RDPU bit is set.
O
DIG External memory interface, Address/Data Bit 1 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 1 input.⁽²⁾
PSP1⁽¹⁾
x
O
DIG PSP read output data (LATD<1>); takes priority over port data.
x
I
TTL PSP write data input.
ECCP3⁽³⁾
0
O
DIG ECCP3 compare and PWM output; takes priority over port data.
1
I
ST ECCP3 capture input.
P3A⁽³⁾
0
O
DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD2/AD2/PSP2 RD2
0
(RD2/CCP4/
1
P3D)
AD2⁽¹⁾
x
O
DIG LATD<2> data output.
I
ST PORTD<2> data input; weak pull-up when RDPU bit is set.
O
DIG External memory interface, Address/Data Bit 2 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 2 input.⁽²⁾
PSP2⁽¹⁾
x
O
DIG PSP read output data (LATD<2>); takes priority over port data.
x
I
TTL PSP write data input.
CCP4⁽³⁾
0
O
DIG CCP4 compare output and PWM output; takes priority over port data.
1
I
ST CCP4 capture input.
P3D⁽³⁾
0
O
DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD3/AD3/
PSP3⁽¹⁾
RD3⁽¹⁾
0
1
O
DIG LATD<3> data output.
I
ST PORTD<3> data input; weak pull-up when RDPU bit is set.
AD3⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 3 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 3 input.⁽²⁾
PSP3⁽¹⁾
x
O
DIG PSP read output data (LATD<3>); takes priority over port data.
x
I
TTL PSP write data input.
RD4/AD4/
RD4⁽¹⁾
0
PSP4/SDO2⁽¹⁾
1
O
DIG LATD<4> data output.
I
ST PORTD<4> data input; weak pull-up when RDPU bit is set.
AD4⁽¹⁾
x
O
DIG External memory interface, Address/Data Bit 4 output.⁽²⁾
x
I
TTL External memory interface, Data Bit 4 input.⁽²⁾
PSP4⁽¹⁾
x
O
DIG PSP read output data (LATD<4>); takes priority over port data.
x
I
TTL PSP write data input.
SDO2⁽¹⁾
0
O
DIG SPI data output (MSSP2 module); takes priority over port data.
Legend:
Note 1:
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
These features or port pins are implemented only on 100-pin devices.
External memory interface I/O takes priority over all other digital and PSP I/O.
These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).
 2011 Microchip Technology Inc.
DS39762F-page 155