PIC18F97J60_11 Datasheet, PDF (116/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

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8.1 External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 8-1). This register is
available in all program memory operating modes,
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/Os.
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 8.5 “Program Memory
Modes and the External Memory Bus”.
The WAIT bits allow for the addition of Wait states to
external memory operations. The use of these bits is
discussed in Section 8.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These operating modes are discussed in more detail in
Section 8.6 “16-Bit Data Width Modes”. The WM bits
have no effect when an 8-Bit Data Width mode is
selected.
REGISTER 8-1:
R/W-0
EBDIS
bit 7
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
U-0
R/W-0
R/W-0
U-0
—
WAIT1
WAIT0
—
U-0
R/W-0
—
WM1
R/W-0
WM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
EBDIS: External Bus Disable bit
1 = External bus is enabled when microcontroller accesses external memory; otherwise, all external
bus drivers are mapped as I/O ports
0 = External bus is always enabled, I/O ports are disabled
Unimplemented: Read as ‘0’
WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
Unimplemented: Read as ‘0’
WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: WRH is active when TABLAT is written to and TBLPTR contains an odd
address. When TBLPTR contains an even address, writing to TABLAT loads a holding latch with
the value written.
01 = Byte Select mode: TABLAT data is copied on both MSB and LSB; WRH and (UB or LB)
will activate
00 = Byte Write mode: TABLAT data is copied on both MSB and LSB; WRH or WRL will activate
DS39762F-page 116
 2011 Microchip Technology Inc.