PIC18F97J60_11 Datasheet, PDF (32/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ4
39
I/O
ST
Digital I/O.
RJ5
40
I/O
ST
Digital I/O
VSS
11, 31, 51, 70 P
— Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
— Positive supply for peripheral digital logic and I/O pins.
AVSS
26
P
— Ground reference for analog modules.
AVDD
25
P
— Positive supply for analog modules.
ENVREG
24
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
Core logic power or external filter capacitor connection.
P
—
Positive supply for microcontroller core logic
(regulator disabled).
P
—
External filter capacitor connection (regulator enabled).
VSSPLL
67
P
— Ground reference for Ethernet PHY PLL.
VDDPLL
66
P
— Positive 3.3V supply for Ethernet PHY PLL.
VSSTX
64
P
— Ground reference for Ethernet PHY transmit subsystem.
VDDTX
61
P
— Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX
57
P
— Ground reference for Ethernet PHY receive subsystem.
VDDRX
60
P
— Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS
65
I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+
63
O
— Ethernet differential signal output.
TPOUT-
62
O
— Ethernet differential signal output.
TPIN+
59
I Analog Ethernet differential signal input.
TPIN-
58
I Analog Ethernet differential signal input.
Legend:
Note 1:
2:
3:
4:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
DS39762F-page 32
 2011 Microchip Technology Inc.