PIC18F97J60_11 Datasheet, PDF (193/492 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
69
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
70
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
71
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
71
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
71
PIR2
OSCFIF CMIF ETHIF
r
BCL1IF
—
TMR3IF CCP2IF
71
PIE2
OSCFIE CMIE ETHIE
r
BCL1IE
—
TMR3IE CCP2IE
71
IPR2
OSCFIP CMIP ETHIP
r
BCL1IP
—
TMR3IP CCP2IP
71
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
71
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
71
IPR3
TRISG
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
71
TRISG7 TRISG6 TRISG5 TRISG4 TRISG3⁽¹⁾ TRISG2 TRISG1 TRISG0
71
TMR1L
Timer1 Register Low Byte
70
TMR1H
Timer1 Register High Byte
70
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70
TMR3H
Timer3 Register High Byte
70
TMR3L
Timer3 Register Low Byte
70
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71
CCPR4L Capture/Compare/PWM Register 4 Low Byte
72
CCPR4H Capture/Compare/PWM Register 4 High Byte
72
CCPR5L Capture/Compare/PWM Register 5 Low Byte
73
CCPR5H Capture/Compare/PWM Register 5 High Byte
73
CCP4CON
—
—
DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 73
CCP5CON
—
—
DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 73
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by Capture/Compare, Timer1 or
Timer3.
Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ‘0’.
 2011 Microchip Technology Inc.
DS39762F-page 193